The present invention relates to an overcurrent protection circuit which stops the flow of a current to a load at the time of overcurrent detection without an erroneous operation caused by an inrush current and the like.
FIG. 1 is a view showing an overcurrent protection circuit in the related art. Rs is a load current detection resistor, and Qm is a P-channel MOS field effect transistor. These are connected in series to a power source B and a load RL. A first transistor Q10 switches between ON and OFF states depending on a voltage drop which occurs at both ends of the load current detection resistor Rs according to a load current, which is a current supplied to the load.
When the power source B is turned on, the voltage of the power source B is divided by resistors R100 and R110, and a predetermined voltage is applied to a control end of the main transistor Qm. If a voltage is applied to the control end of the main transistor Qm, the main transistor Qm is turned on so that a necessary current is supplied to the load RL.
Since the load resistance is reduced if a ground fault occurs in a load-side circuit, excessive current flows through both the load current detection resistor Rs and the main transistor Qm. If this overcurrent exceeds the allowable amount of current of the device, the load current detection resistor Rs and the main transistor Qm break down.
When an overcurrent flows, a result of the voltage drop in the load current detection resistor Rs reaches an overcurrent detection voltage set beforehand and the first transistor Q10 is turned on accordingly. Through the turning ON of the first transistor Q10, a current flows through resistors R10 and R20. Then, a bias voltage is applied between the control and output ends of a second transistor Q20 to turn on the second transistor Q20. In addition, a current flows through resistors R40 and R50 through the turning on of the second transistor Q20. Then, a bias voltage is applied between the control and input ends of a third transistor Q30 to turn on the third transistor Q30. Moreover, through the turning on of the third transistor Q30, a potential difference between the input and control ends of the main transistor Qm is reduced to turn off the main transistor Qm. Thus, the overcurrent protection circuit in the related art is configured such that when the occurrence of an overcurrent is detected, the flow of the overcurrent is stopped by the turning OFF of the main transistor Qm.
In addition, a rising time of the voltage applied to the control end of the second transistor Q20 is delayed by the time constant of an integrating circuit which is formed by a resistor R30 and a capacitor C10. For this reason, even when an instantaneous overcurrent is generated due to an inrush current at the start of operation or the input of noise from the outside, the second transistor Q20 is not turned on immediately. Thus, the overcurrent protection circuit in the related art is configured such that the flow of current is not stopped due to erroneously detecting an inrush current at the start of operation or the like as a ground fault (see, JP-A-2000-175345).
However, the overcurrent protection circuit in the related art has the following problems.
If an overcurrent is detected, the overcurrent protection circuit stops the flow of the overcurrent in a set time, which is specified by the time constant of the capacitor C10. However, since the flow of the overcurrent continues during the set time, there is a possibility that the load current detection resistor Rs and the main transistor Qm connected to the load will break down during the time.
For this reason, expensive components, for which the allowable amount of current is high and are capable of withstanding an overcurrent over the set time, should be used for both of the elements. Accordingly, there is a problem that the cost of the overcurrent protection circuit increases.